CMOS technology is used to construct various types of integrated circuits (ICs). CMOS technology is used in microprocessors, microcontrollers, memory devices, (e.g., random access memory (RAM)), and other digital logic circuits. Typically, a CMOS circuit uses complementary and symmetrical pairs of n-type channel metal-oxide-semiconductor (NMOS) and p-type channel metal-oxide-semiconductor (PMOS) transistors. Since only one of the NMOS or PMOS transistors are used at any given time, the CMOS circuit requires less power than a circuit using only one transistor type.
For example, FIG. 1A shows a simple conventional CMOS circuit 100 that includes two NOR gates 102 and 104. The NOR gate 102 includes PMOS transistors 106 and 108, and NMOS transistors 110 and 112. The NOR gate 104 includes PMOS transistors 114 and 116, and NMOS transistors 118 and 120. The CMOS circuit 100 further includes NMOS transistors 122 and 124, a negative power supply terminal (Vss) 126, a positive power supply terminal (Vdd) 128, inputs 130, 132 and 134, outputs 136 and 138, and a parasitic net (i.e., wire, connection) 140. Each of the transistors 106, 108, 110, 112, 114, 116, 118, 120, 122 and 124 includes a gate terminal A, a source terminal B and a drain terminal C.
FIG. 1B shows a symbolic circuit associated with the functionality of the conventional CMOS circuit 100 of FIG. 1A, whereby the NOR gates 102 and 104 share the input 132.
The output 136 of the NOR gate 102 is either a logic 1 or a logic 0 based on the inputs 130 and 132 in accordance with Table 1 below.
TABLE 1Input 130 ofInput 132 ofOutput 136 ofNOR gate 102NOR gate 102NOR gate 102001010100110
As shown in FIG. 1A, the PMOS transistors 106 and 108 of the NOR gate 102 are connected in series, (i.e., they form a PMOS stack 106/108), whereby the source terminal 106B is connected to Vdd 128, the drain terminal 106C is connected to the source terminal 108B, and the drain terminal 108C is connected to the output 136. The NMOS transistors 110 and 112 are connected in parallel, whereby the source terminals 110B and 112B are connected to Vss 126, and the drain terminals 110C and 112C are connected to the output 136. As indicated in Table 1 above, if either or both of the inputs 130 and 132 of the NOR gate 102 is a logic 1, either or both of the NMOS transistors 110 and 112 is turned on, causing the output 136 to be a logic 0. In order for the output 136 to be a logic 1, both of the inputs 130 and 132 must be a logic 0, which turns on both of the PMOS transistors 106 and 108 and allows Vdd 128 to pass through the stack 106/108, while at the same time turning of the NMOS transistors 110 and 112.
The output 138 of the NOR gate 104 is either a logic 1 or a logic 0 based on the inputs 132 and 134 in accordance with Table 2 below.
TABLE 2Input 132 ofInput 134 ofOutput 138 ofNOR gate 104NOR gate 104NOR gate 104001010100110
As shown in FIG. 1A, the PMOS transistors 114 and 116 of the NOR gate 104 are connected in series, (i.e., they form a PMOS stack 114/116), whereby the source terminal 114B is connected to Vdd 128, the drain terminal 114C is connected to the source terminal 116B, and the drain terminal 116C is connected to the output 138. The NMOS transistors 118 and 120 are connected in parallel, whereby the source terminals 118B and 120B are connected to Vss 126, and the drain terminals 118C and 120C are connected to the output 138. As indicated in Table 2 above, if either or both of the inputs 132 and 134 of the NOR gate 104 is a logic 1, either or both of the NMOS transistors 118 and 120 is turned on, causing the output 138 to be a logic 0. In order for the output 138 to be a logic 1, both of the inputs 132 and 134 must be a logic 0, which turns on both of the PMOS transistors 114 and 116 and allows Vdd 128 to pass through the stack 114/116, while at the same time turning of the NMOS transistors 118 and 120.
The inputs 130, 132 and 134 to the CMOS circuit 100 are typically provided on a monotonic (i.e., clocklike) basis, rather than on a static basis, whereby each input's logic value (1 or 0) undergoes a transition each cycle. The outputs 136 and 138 are typically used to drive a dynamic logic circuit, (e.g., an NMOS device, register file, and the like). If the NMOS transistors 122 and 124 were not in the CMOS circuit 100, a problem of glitching may occur due to the net 140 exhibiting a parasitic capacitance.
For example, the parasitic capacitance exhibited by the net 140 may be affected by the condition where the PMOS transistor 108 is turned on by a logic 0 at the input 130. Thus, a charge accumulating on the net 140 would be transferred through the PMOS transistor 108 to the output 136, which may cause glitching even though the output 136 should have a logic 0 value because the input 132 has a logic value of 1. The size of the charge that is transferred may be affected by the amount of charge stored on the net 140, as well as the amount of capacitance on the net 140 and on the output 136. However, the NMOS transistors 122 and 124 in the CMOS circuit 100 serve as a net pulldown circuit that solves this potential output glitching problem by discharging the net 140 when the input 132 is a logic 1.
Thus, a CMOS circuit is needed that can avoid the glitching problem described above with respect to the example conventional CMOS circuit of FIGS. 1A and 1B.